1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device having a metal-insulator-metal (MIM) capacitor including multiple metal lines, and a method for fabricating the same.
2. Description of Related Art
Methods for integrating capacitors having large capacitance in semiconductor devices have been studied for increasing the performance of analog circuits and radio frequency (RF) devices needing high-speed operation. When a lower electrode and an upper electrode of a capacitor are formed of a doped polysilicon, a natural oxide layer is produced by an oxidation reaction occurring at interfaces between the lower electrode and a dielectric film and between the dielectric film and the upper electrode, thereby decreasing the capacitance. A capacitor having a metal-insulator-silicon (MIS) or a metal-insulator-metal (MIM) structure may be used to prevent this decrease in capacitance. MIM capacitors are typically employed in high performance semiconductor devices because MIM capacitors exhibit low specific resistance and a lack of parasitic capacitance caused by depletion.
In a method for fabricating a semiconductor device having a MIM capacitor, as shown in FIG. 1, a metal layer of about 6000 Å is formed on an insulating layer 10. The metal layer is patterned to form a lower metal line 15 and a lower electrode 20 of the MIM capacitor at the same level. A dielectric film 40 is coated thereon. A metal is deposited over the dielectric film 40 to a thickness of more than 1500 Å and patterned to form an upper electrode 50 on the dielectric film 40. An inter-metal-dielectric (IMD) layer 60 is formed on the dielectric film 40 and the upper electrode 50. A first via 70 connected to the lower metal line 15, a second via 72 connected to the lower electrode 20, and a third via 74 connected to the upper electrode 50 are formed in the IMD layer 60. A metal is deposited to a thickness of about 3000 Å on the IMD layer 60. The metal is patterned thereby forming upper metal lines 80, 82, and 84 respectively connected to the first, second, and third vias 70, 72, and 74.
The step of forming the upper dielectric includes a plasma etch which damages the surface of the dielectric film 40 since the upper electrode 50 is patterned over the dielectric film 40. Further, since the depth of the first and second vias 70 and 72 differs from that of the third via 74, an etching process with a significantly high selectivity is needed. If the first and second vias 70 and 72, and the third via 74 are formed separately, another mask is needed, thereby complicating the etching process.
When a single mask process is used, since the depth of the first and second vias 70 and 72 is greater than the depth of the third via 74, the upper electrode 50 underlying the third via 74 is over etched. The dielectric film 40 may be damaged and the underlying lower electrode 20 is exposed by the etch, so that an electric short is likely to occur between the upper electrode 50 and the lower electrode 20 once the upper metal lines 82 and 84 are respectively connected to the second and third vias 72 and 74. Because the over etch is affected by variable factors in the single mask process, the contact resistances of the vias may differ among devices or among the vias in a device, thus increasing the dispersion of characteristics of devices.
Therefore, a need exists for an upper electrode formed with a thickness sufficient to withstand etching of an IMD layer for forming a third via.